This invention relates in general to the field of manufacturing electronic devices and more particularly to an improved method for integrated circuit layout and verification.
Integrated circuit designers are constantly striving to make the individual features within integrated circuits smaller so that the device density of the overall system can be improved. The photolithographic processes used to form devices in an integrated circuit have reached a point where the feature size is comparable or even smaller than the wavelength of the light used to transfer the mask pattern onto the photoresist used to create the features. In order for such a feature to be created under such conditions, the photo mask used to create the feature must be altered to correct for nonlinear behavior of light and etch interactions during the patterning of integrated circuits. This process is referred to as proximity correction and it occurs after the completion of the layout of the mask pattern. The theoretical mask pattern can be proximity corrected using an iterative process that accounts for the multitude of different interactions that cause distortions and variations from the desired pattern which is to be reproduced on the integrated circuit substrate. The interactions that cause these distortions include the limited band pass of the optical system to reproduce high spacial frequency mask components, optical variations and aberrations in the lens of the imaging system, reflectivity effects and local surface scattering variations of the image, standing wave effects, interference of light and local area background effects, thin film effects, resist development effects and etch loading effects.
The implementation of proximity correction methods can result in the alteration of the theoretical shapes within the mask. Borders of features can be expanded or contracted in order to account for the various effects discussed. This alteration of the borders of features can result in erroneous results when the altered mask is tested for various design rules and electrical characteristics.
Accordingly, a need has arisen for an integrated circuit layout verification technique that allows for the use of proximity correction but eliminates disadvantages associated with conventional methods of mask verification.
Accordingly, an integrated circuit layout mask verification method is provided that substantially eliminates or reduces disadvantages associated with conventional methods of applying proximity correction.
According to one embodiment of the present invention, a method is provided that comprises the steps of creating a data set defining a mask layout. This data set is then corrected using proximity correction algorithms. A data set is then generated comprising the theoretical contours of the features which would result from the use of the contour corrected mask data. This contour data set is then bounded. The bounded contour data set is then compared to the theoretical mask layout data and tested against various design rules.
An important technical advantage of the present invention inheres in the fact that it allows for the use of proximity correction methods but generates a bounded contour data set that can be used to check the layout for electrical efficacy and compliance with various design rules. In this manner, proximity correction can be used to avoid a failure of a theoretical layout which would not have been apparent with said layout prior to construction of the integrated circuit.